08. Distributed AI Parallelism Paradigms: Data Parallelism (DP), Tensor Parallelism (TP), Pipeline Parallelism (PP) • AI Infrastructure, GPU Serving & MLOps (CUDA, Triton, TGI) • Rishabh Ki Kaksha

AI Infrastructure, GPU Serving & MLOps (CUDA, Triton, TGI) › 08. Distributed AI Parallelism Paradigms: Data Parallelism (DP), Tensor Parallelism (TP), Pipeline Parallelism (PP)

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Course Syllabus

Module 1: GPU Architecture, CUDA Internals & Hardware Hierarchy

01. NVIDIA GPU Architecture: Streaming Multiprocessors (SMs), Tensor Cores, CUDA Cores & HBM3 Memory Bandwidth 02. GPU Memory Hierarchy: Registers, Shared Memory (SRAM), L1/L2 Caches & High-Bandwidth VRAM 03. CUDA Programming Basics: Writing Custom GPU Kernels in C++/CUDA & Triton Python DSL

Part 1: GPU Acceleration, Serving & Production Guardrails

Module 2: High-Performance LLM Serving Engines (vLLM, TGI, Triton)

04. The KV Cache Bottleneck: Memory Footprint Calculations & PagedAttention Virtual Memory Architecture 05. Dynamic & Continuous Batching (Iteration-Level Scheduling) vs Static Batching in LLM Serving 06. Production Benchmark: vLLM vs HuggingFace TGI (Text Generation Inference) vs NVIDIA Triton Inference Server 07. Speculative Decoding & Medusa Multi-Head Decoding for 2-3x Faster Token Generation

Module 3: Multi-GPU & Distributed Inference: Tensor & Pipeline Parallelism

08. Distributed AI Parallelism Paradigms: Data Parallelism (DP), Tensor Parallelism (TP), Pipeline Parallelism (PP) 09. Tensor Parallelism in Action: Megatron-LM Matrix Splitting across NVLink & NVSwitch Networks 10. DeepSpeed & PyTorch FSDP (Fully Sharded Data Parallel): Zero Redundancy Optimizer (ZeRO-1, ZeRO-2, ZeRO-3)

Module 4: MLOps Pipelines: Model Registry, Experiment Tracking (MLflow/W&B)

11. MLOps Foundations: Model Versioning, Artifact Registries & Lineage Tracking with MLflow and Weights & Biases 12. Automated Continuous Training Pipelines with Kubeflow Pipelines & GitHub Actions CI/CD for AI Models 13. Feature Stores in Production (Feast): Real-Time Online Feature Retrieval vs Offline Batch Processing

Module 5: Kubernetes GPU Orchestration, Auto-Scaling & Continuous Observability

14. Kubernetes for AI Workloads: NVIDIA GPU Operator, Device Plugins & Time-Slicing vs Multi-Instance GPU (MIG) 15. Horizontal Pod Auto-Scaling (HPA) for LLM Services based on TTFT (Time to First Token) & Queue Depth 16. Serverless GPU Architecture: Ray Serve, Modal & RunPod for Auto-Scaling AI APIs with Zero Cold Starts 17. Observability for GenAI: OpenLLMetry, Arize Phoenix, Langfuse & Prometheus GPU Utilization Metrics 18. Enterprise Cloud Cost Optimization: Spot GPU Instances, Multi-Cloud Orchestration & Slicing VRAM Costs

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# 08. Distributed AI Parallelism Paradigms: Data Parallelism (DP), Tensor Parallelism (TP), Pipeline Parallelism (PP)

> AI Infrastructure & MLOps Notes by Rishabh - Topic 08

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### 1. 3D Parallelism in Trillion-Parameter LLM Clusters 🌐

When a model (e.g. Llama 3 405B) cannot fit on a single GPU (Requires ~800GB VRAM):

```
┌─────────────────────────────────────────────────────────────┐
│ 1. TENSOR PARALLELISM (TP) : Splits single layer across GPUs│
├─────────────────────────────────────────────────────────────┤
│ 2. PIPELINE PARALLELISM(PP): Splits layers across GPU nodes │
├─────────────────────────────────────────────────────────────┤
│ 3. DATA PARALLELISM (DP)   : Replicates model across batches│
└─────────────────────────────────────────────────────────────┘
```

$$\text{Total GPUs} = \text{TP} \times \text{PP} \times \text{DP}$$
$$\text{Example: } 8\ (\text{TP}) \times 4\ (\text{PP}) \times 16\ (\text{DP}) = 512 \text{ GPUs (H100 SuperPOD!)}$$

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### 2. Master Comparison Matrix

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### 3. Interview Ke 3 Sawal Is Topic Se

1. **Pipeline Bubble (Idle GPU time in PP) kya hoti hai?** -> 1F1B (One Forward, One Backward) scheduling schedule use karke micro-batches interleave karna taaki pipeline bubble $< 10\%$ ho jaye.
2. **TP ko single node (8 GPUs) ke andar hi restrict kyu kiya jata hai?** -> Kyunki TP har forward pass me All-Reduce communication karta hai jo cross-node network ethernet par slow ho jata hai; NVLink intra-node speeds support karta hai.
3. **Sequence Parallelism (Megatron-SP) TP ke sath kya optimize karta hai?** -> LayerNorm aur Dropout layers ko sequence dimension ke along split karke residual activations memory reduce karna.

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**Next Topic:** 09. Tensor Parallelism in Action: Megatron-LM Matrix Splitting across NVLink & NVSwitch Networks

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